第一阶段
部分 1
1 Introduction to the Virtuoso Analog Design Environment
2 Schematic Entry
3 Analog Simulation
4 Displaying Simulation Results
5,
关于版图一些基本知识；
部分 2 :?Virtuoso Custom Design Platform 6.14
l?????????IC61 Virtuoso Schematic Editor L/XL presentation, Lei Song;
?????????????????? ? -new features introduction
l?????????IC61 Analog Design Environment L/XL presentation, Lei Song;
?????????????????????-new features introduction
l?????????IC61 Virtuoso Layout Suite L/XL/GXL?presentation,?Amy Zhang;
???????????????????? -new features introduction
???????????????????? -Live demo of?IC61 Virtuoso Layout Suite?L/XL/GXL,Amy Zhang;
l?????????Workshop of Virtuoso Layout Suite XL?.
?
部分 3 :?Virtuoso MMSIM10.1 Overview
l?????????MMSIM10.1 Presentation, Lei Song;
??????????????????-new features introduction
l?????????Workshop of Virtuoso?MMSIM10.1.
部分 4
5 Analyzing Simulation Results
6 Parametric Analysis
7 Using the OCEAN and SKILL Languages
8 Corners Analysis
部分 5
9 Monte Carlo Analysis
10 Component Description Format(CDF)
11 Macromodels, Subcircuits, andInline Subcircuits
12 Hierarchy Editor
13 Inherited Connections
? ??Layout generation
?
??Editing?Virtuoso XL placement
?
??Creating interconnect in Virtuoso?XL
??Using the Wire?Editor
?
??Analyzing and updating data
?
??Working with hierarchical designs and variables
??Generating?abstracts
??Floor planning with Virtuoso?Preview
??Virtuoso Custom Placer setup
??Pin placement with Virtuoso Custom Placer
??Placement?planning and the auto placer
?第二阶段
1,
后端设计关于DRC检测和LVS验证的整个流程；
2,
GDS文件和TF库文件的导入；
3,
关于Cadence Virtuoso库文件的配置；
4,DRC检测的规则；
5,版图设计中的一些寄生效应及其消除方法；
6,其他高级布线的技巧与经验总结。 |
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