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  Synopsys SystemVerilog VMM培训
   入.学.要.求

        学员学习本课程应具备下列基础知识:
        ◆ 电路系统的基本概念。

   班.级.规.模.及.环.境
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
最近开课时间(周末班/连续班/晚班)
Synopsys SystemVerilog VMM培训:2021年9月6日(请抓紧报名)
   实验设备
     ☆资深工程师授课

        
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   .最.新.优.惠.
       ◆在读学生凭学生证,可优惠500元。
   .质.量.保.障.

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、培训结束后免费提供半年的技术支持,充分保证培训后出效果;
        3、培训合格学员可享受免费推荐就业机会。

  Synopsys SystemVerilog VMM培训
培训方式以讲课和实验穿插进行

课.程.描.述 :

?SystemVerilog Verification Using VMM Methodology

OVERVIEW

In this hands-on workshop, you will learn how to develop a VMM SystemVerilog test environment structure which can implement a number of different test cases with minimal modification. Within this VMM environment structure, you will develop stimulus factories, check and coverage callbacks, message loggers, transactor managers, and data flow managers. Once the VMM environment has been created, you will learn how to easily add extensions for more test cases.
After completing the course, you should have developed the skills to write a coverage-driven random stimulus based VMM testbench that is robust, re-useable and scaleable.

?

OBJECTIVES

At the end of the course you should be able to:

??Develop an VMM environment class in SystemVerilog?
??Implement and manage message loggers for printing to terminal or file?
??Build a random stimulus generation factory?
??Build and manage stimulus transaction channels?
??Build and manage stimulus transactors
??Implement checkers using VMM callback methods?
??Implement functional coverage using VMM callback methods

?

AUDIENCE PROFILE

Design or Verification engineers who develop SystemVerilog testbenches using VMM base classes.

?

PREREQUISITES

To benefit the most from the material presented in this workshop, students should:

Have taken the SystemVerilog Testbench workshop

OR

Possess equivalent knowledge of SystemVerilog testbench including:
??Creating/Using SystemVerilog interfaces?
??How to encapsulate testbench components in SystemVerilog class structure
??Familiarity with SystemVerilog class inheritance
??Creating/Using System Verilog queues?
??Creating Cover Group for functional coverage

?

COURSE OUTLINE

?

Unit 1?
??SystemVerilog class inheritance review
??VMM Environment?
??Message Service
??Data model

?

Unit 2
??Stimulus Generator/Factory?
??Check & Coverage
??Transactor Implementation?
??Data Flow Control?
??Scenario Generator?
??Recommendations