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   Synopsys IC Compiler培训
   班.级.规.模.及.环.境
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
最近开课时间(周末班/连续班/晚班)
Synopsys IC Compiler培训:2021年9月6日(请抓紧报名)
   实验设备
     ☆资深工程师授课

        
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        ☆合格学员免费推荐工作


        专注高端培训17年,曙海提供的课程得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

        ★实验设备请点击这儿查看★
   .最.新.优.惠.
       ◆在读学生凭学生证,可优惠500元。
   .质.量.保.障.

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、培训结束后免费提供半年的技术支持,充分保证培训后出效果;
        3、培训合格学员可享受免费推荐就业机会。

  Synopsys IC Compiler培训

培训方式以讲课和实验穿插进行。

IC Compiler 1?

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Overview
The workshop starts out with a high-level introduction to IC Compiler? graphical user interface, during which you will learn about the 3 core commands place_opt, clock_opt, and route_opt, as well as the more targeted atomic commands for more specific needs.

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You will learn the details of design and timing setup, including setting up physical and logical libraries, importing design formats and floorplans, and setting the design up for proper timing analysis.

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The workshop goes in-depth into using IC Compiler to perform placement, power optimization, scan optimization, clock tree synthesis and routing operations, including interleaved logic optimizations. You will also learn how to perform Design-for-Manufacturing tasks in IC Compiler, including antenna fixing, via doubling, metal filling, and critical area optimization. Another unit is dedicated to the topic of the new Multi Scenario capabilities, including how to apply SDC constraint files and operating conditions and how to perform analysis and optimization in parallel. The unit will also show you the advantages of using on-chip-variation mode.

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The class explores the new Design Planning features in IC Compiler, which support full flat floorplanning including automatic macro placement, power network synthesis and analysis, and prototype route and optimization.

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The workshop is accompanied by comprehensive hands-on labs, which provide an opportunity to apply all concepts covered during the lectures.

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Objectives?
At the end of this workshop the student should be able to:?
?? Read necessary files required to run IC Compiler, resolving common errors/warnings?
?? Set up timing for analysis and optimizations?
?? Perform placement and optimizations?
?? Analyze congestion maps and reports?
?? Perform power optimization?
?? Perform scan reordering using ScanDEF?
?? Set up the design for clock tree synthesis?
?? Perform clock tree synthesis and post-CTS optimizations?
?? Analyze timing and clock specifications post CTS?
?? Route the design using the core and atomic commands?
?? Describe the need for Multi-corner, Multi-Mode analysis, and optimization?
?? Specify a scenario in IC Compiler?
?? Analyze the design for SI and perform SI optimizations?
?? Perform unconstrained and freeze silicon ECOs?
?? Perform antenna fixing, via doubling, metal filling, filler cell insertion, critical area optimization?
?? Create a flat floorplan including core and IO area setup, power network synthesis and routing, timing driven macro placement?
?? Perform power network analysis and virtual pad insertion?

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Audience Profile
ASIC, back-end,?or?layout designers with experience in standard-cell-based automatic Place and Route.

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Prerequisites
To benefit the most from the material presented in this workshop, students should have working knowledge of Physical Design using Physical Compiler, Astro,?or?any other physical design tool.

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Course Outline?

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Unit 1?
?? Introduction?
?? IC Compiler Basic Flow?
?? Design Planning?

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Unit 2?
?? Placement, Power and Test?
?? Clock Tree Synthesis?

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Unit 3?
?? Multi Scenario Optimization?
?? Routing and Signal Integrity?
?? Chip Finishing and DFM?