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   SoC Encounter RTL-to-GDSII物理实现
   班.级.规.模.及.环.境
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
最近开课时间(周末班/连续班/晚班)
SoC Encounter RTL-to-GDSII物理实现:2021年9月6日(请抓紧报名)
   实验设备
     ☆资深工程师授课

        
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        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、培训结束后免费提供半年的技术支持,充分保证培训后出效果;
        3、培训合格学员可享受免费推荐就业机会。

  SoC Encounter RTL-to-GDSII物理实现

 

培训安排:

第一阶段:

概述

SOCEncounter的基本界面操作

布图(Floorplan)

电源网络设计(power?plan)

布局(Placement)

扫描链重排与优化(Scan?Chain?Re-ordering)

早期布线特性分析(TrialRoute)

1) Advance and High performance design challenged– Encounter solution-RCP

Traditional synthesis tools use vendor-supplied wire-load models based on fanouts, which do not provide accurate wire delay information especially for designs where a significant portion of the delays are contributed by the wires. The RCP flow uses a complete placement and considers congestion and legal placement as a cost function during the RTL-to-gates phase, to create a better netlist. This flow ensures both the best accuracy and the most predictable closure with back-end tools.

-CCOPT

Clock Concurrent Optimization technology, also known as CCopt, which delivers superior capabilities for designers faced with increasing performance, power and area challenges. Specifically, ccopt technology has delivered significant quality of silicon (QoS) on high-speed processor designs in the areas of:

n ?Power (clock tree power reduction up to 30 percent and total power improvements of up to 10 percent),

?

n ?Performance (improvements of up to 100 MHz for a GHz design), and

n ?Area (clock tree area reduction up to 30 percent)

-GigaOpt

The new GigaOpt technology inside EDI System produces high-quality results faster than traditional optimization engines by harnessing the power of multiple CPUs. GigaOpt does multi-threading combined base and SI delay timing optimization.

2) ?Mixed Signal Physical Implementation flow

- Introduction

- Integration Constraints

- Netlist Driven Mixed Signal Flow

3) ?RDL co-design flow

- Flipchip introduce

- Encounter Flipchip flow

- RDL co-design



In this course, you willRun timing optimization?
Run silicon virtual prototyping?
Run placement with the Amoeba placer?
Estimate parasitics and generate delay information?
Analyze congestion after running Trial Route?
Create clock trees?
Create physical partitions (hierarchy) and timing budgets?
Run signal integrity analysis?
Optimize timing?
Run NanoRoute? Ultra detail routing?
Apply postroute timing and signal integrity optimization
In this course, you will get a high-level technical overview of the SoC Encounter flow. However, to gain in-depth knowledge about each tool, refer to the Related Courses list and take the corresponding course(s).

l Laker structure、Environment setup、Viewing design
l Basic drawing、Technology File、Import & Export design
l Customize your LAKER、DRC & Third-Party Integration link
Laker L2 Training
l Rule-Driven、Magic cell、User Define Device (UDD)、Path Finder
l P2P router、Route by Label、Laker Advance Function

   Synthesis flow?
   Application of design constraints?
   Optimization strategies?
?
   Synthesis of datapath structures?
   Synthesis for low power?
   Interface to place and route?
   Design for testability (optional)?

第二阶段:

q Selecting and Highlighting Objects in the Design

q Floorplanning the Design

q Planning Power?

q Running Detail Placement

q Scan Optimization and Reordering

q Analyzing Route Feasibility with?Trial Route

q Extracting Parasitics and Analyzing Timing

q Multi-Mode Multi-Corner Analysis

q Optimizing and Closing Timing

q Implementing the Clock Tree

q Routing Power with?Special Route

q Analyzing Power Routing Optimization

q Routing for Signal Integrity, Timing, and Design for Yield

q Evaluating Routing Problems

q Wire Editing

q Signal Integrity

寄生参数提取和静态时序分析(Extraction?and?STA)

多模多角分析(MMMC)

时序优化(Timing?Optimization)

时钟树生成(CTS)

电源网络布线(Special?Route)

功耗分析(Power?Analysis)

第三阶段:Laker Schematic Driven Layout Training

Laker SDL 流程介绍
Laker L3 实例教程
练习一:Laker-L3的基本接口操作
练习二:如何将Design读进Laker L3
练习三:Layout的绘制与Stick Diagram的运用
练习四:Laker Net Router的操作
练习五:Matching Creation的运用
练习六:重复电路的画法(Copy Associate & Pattern Reuse)
练习七:ECO的运用