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  FPGA设计执行培训课程
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FPGA设计执行培训课程:2021年9月6日(请抓紧报名)
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  FPGA设计执行培训课程
培训方式以讲课和实验穿插进行

课.程.描.述 :

第一阶段 Advanced FPGA Synthesis using Synplify Pro & Synplify Premier

Overview
This course first introduces new users to the Synplify Pro and Synplify Premier tools. Designers can take this course at their own pace and enjoy the online version of this class. Comprehensive notes complete the information displayed on each page. This course is powered by Vitalect.

Objectives
The course will familiarize new students with the FPGA design flow utilizing features of the Synplify Pro product, enabling them to actively create designs using the Synplify Pro product. The course then expands on these concepts to focus on complex design techniques, debugging and high-performance design, as well as physical synthesis.

Audience Profile
Designers who wish to maximize the performance of their designs, or learn more powerful design techniques using the Synplify Pro and Synplify Premier tools.

Prerequisites
Knowledge of logic synthesis and FPGA technologies.

Course Outline
  • Getting Started
  • Timing Optimizations
  • Design Analysis and Debugging
  • Handling IPs
  • Xilinx Specific Topics
  • Altera Specific Topics
  • Actel Specific Topics
  • Lattice Specific Topics
  • Synplify Premier Physical Synthesis For Xilinx
  • Synplify Premier Design Planner for Xilinx
  • Synplify Premier Physical Synthesis for Altera

第二阶段 Advanced FPGA Debugging with the Identify Tool?

Overview
This course introduces concepts on full-speed hardware debugging using the Identify toolset which provides an embedded HDL analyzer with debug access at the RTL level similar to an RTL simulator. Designers can take this course at their own pace and enjoy the online version of this class. Comprehensive notes complete the information displayed on each page. This course is powered by Vitalect.

Objectives
The course focuses on understanding concepts on instrumenting the design and using the Identify product to successfully verify the functionality of hardware.

Course Outline

  • Identify Instrumentor
  • IICE
  • Identify Debugger
  • Advanced Debugging

第三阶段 Asic Prototyping with the Certify? Tool?

Overview
This course introduces concepts on ASIC prototyping using the Certify ASIC Prototyping tool. Designers can take this course at their own pace and enjoy the online version of this class. Comprehensive notes complete the information displayed on each page. This course is powered by Vitalect.

Objectives
The focus will be on understanding concepts on RTL-level partitioning, and using the Certify product to create a successfully partitioned design. Students will learn:
  • Certify Product Concepts
  • Understanding the Certify UI
  • Specification of Prototype Board Descriptions
  • Partitioning to FPGA Devices

Course Outline

  • Project Management
  • RTL Prototyping Concepts
  • Defining a Board Description File
  • Quick Partitioning Technology
  • Advanced Partitioning Tools
  • Area Estimation
  • Creating a Successful Partition
  • Hierarchical Systems
  • Debug Insertion Features
  • Performing Pin Assignment
  • MultiPoint? Synthesis Flow

第四阶段 Advanced Algorithm Implementation with Synphony Model Compiler

Overview
This course first introduces new users to the Synphony HLS tools. Designers can take this course at their own pace and enjoy the online version of this class. Comprehensive notes complete the information displayed on each page. This course is powered by Vitalect.

Objectives
The course will familiarize new students with the Synphony Model Compiler design flow including model creation, implementation and architectural exploration, enabling them to actively create designs using the Synphony high-level synthesis products. The course then expands on these concepts to focus on more complex modeling and implementation features.

Course Outline

  • Flow Overview
  • Signal Date Types
  • Vector Support
  • Multi-rate Modeling
  • Architectural Synthesis
  • Micro-architectural Optimizations
  • Retiming
  • Folding and Multi-Channelization
  • Advanced Features and IP Functions