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   数字芯片设计和验证培训
   班.级.规.模.及.环.境
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
最近开课时间(周末班/连续班/晚班)
数字芯片设计和验证培训:2021年9月6日(请抓紧报名)
   实验设备
     ☆资深工程师授课

        
        ☆注重质量
        ☆边讲边练

        ☆合格学员免费推荐工作


        专注高端培训17年,曙海提供的课程得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

        ★实验设备请点击这儿查看★
   .最.新.优.惠.
       ◆在读学生凭学生证,可优惠500元。
   .质.量.保.障.

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、培训结束后免费提供半年的技术支持,充分保证培训后出效果;
        3、培训合格学员可享受免费推荐就业机会。

  数字芯片设计和验证培训

培训方式以讲课和实验穿插进行。

Overview
This course covers 2 part of digital IC: Design and Verification.
The first part of this course is an introduction of digital IC design. It gives guidelines on how to set up good coding style for RTL design and how to write RTL for design for different level,from module level to SoC level.
The second part of this course is an introduction to the Incisive Plan-to-Closure Methodology (IPCM). IPCM defines how to perform a verificaiton process by going through plan, execute, measure and react process. It also introduces how to perform the process automatically.This 2 day course shows you how to write HDL code from module to SoC level design. It also provides guidance and practice to perform a coverage-driven-verification process automatically.


Objectives?
In this course, you will:
● Learn how to set up coding style for RTL.?
● Apply the coding style to module-level and SoC-level design?
● Learn how to check coding style?
● Learn a typical verification flow of from plan to closure?
● Learn to implemente the verification process automatically


Course Outline

Unit 1
● Module Level RTL design?
● RTL Coding Style and rule check
● System-On-a-Chip Design

Unit 2
● Verification Methodology
● Verification Plan
● Verification Execute
● Verification Measure
● Verification React
● Verification Process Management


Audience Profile

Design Engineers & Verification Engineers
At least one of the SystemC, VHDL, and Verilog languages SystemVerilog Language and Application? Basic digital IC design, simulation, verification knowledge

?

Synopsys Tools Used?
ncisive® DesignTeam Simulator